commercial temperature range idt74fct388915t 3.3v low skew pll-based cmos clock driver (3-state) 1 august 2004 commercial temperature range the idt logo is a registered trademark of integrated device technology, inc. ? 2004 integrated device technology, inc. dsc-4243/5 features: ? 0.5 micron cmos technology ? input frequency range: 10mhz ? f2q max. spec (freq_sel = high) ? max. output frequency: 150mhz ? pin and function compatible with fct88915t, mc88915t ? 5 non-inverting outputs, one inverting output, one 2x output, one 2 output; all outputs are ttl-compatible ? 3-state outputs ? duty cycle distortion < 500ps (max.) ? 32/?16ma drive at cmos output voltage levels ?v cc = 3.3v 0.3v ? inputs can be driven by 3.3v or 5v components ? available in 28 pin plcc and ssop packages functional block diagram idt74fct388915t 70/100/133/150 3.3v low skew pll-based cmos clock driver (with 3-state) description: the fct388915t uses phase-lock loop technology to lock the fre- quency and phase of outputs to the input reference clock. it provides low skew clock distribution for high performance pcs and workstations. one of the outputs is fed back to the pll at the feedback input resulting in essentially zero delay across the device. the pll consists of the phase/ frequency detector, charge pump, loop filter and vco. the vco is designed for a 2q operating frequency range of 40mhz to f2q max. the fct388915t provides 8 outputs, the q5 output is inverted from the q outputs. the 2q runs at twice the q frequency and q/2 runs at half the q frequency. the freq_sel control provides an additional 2 option in the output path. pll _en allows bypassing of the pll, which is useful in static test modes. when pll_en is low, sync input may be used as a test clock. in this test mode, the input frequency is not limited to the specified range and the polarity of outputs is complementary to that in normal operation (pll_en = 1). the lock output attains logic high when the pll is in steady-state phase and frequency lock. when oe/ rst is low, all the outputs are put in high impedance state and registers at q, q and q/2 outputs are reset. the fct388915t requires one external loop filter component as recommended in figure 3. phase/freq. detector m u x 0 1 sync (0) feedback sync (1) ref_sel pll_en mux 01 divide -by-2 ( 1) ( 2) 1 0 m u x charge pump voltage controlled oscilator oe/rst freq_sel 2q q0 q1 q2 q3 q4 q5 q/2 r d q cp q lf lock r d q cp r d q cp r d q cp r d q cp r d q cp r d q cp
commercial temperature range 2 idt74fct388915t 3.3v low skew pll-based cmos clock driver (3-state) pin configuration pin description o e / r s t v c c q 5 g n d q 4 v c c 2 q q/2 gnd q3 v cc q2 gnd lock p l l _ e n g n d q 1 v c c q 0 g n d f r e q _ s e l feedbk ref_sel sync(0) v cc (an) lf gnd(an) sync(1) 28 4321 2726 25 24 23 22 21 20 19 5 6 7 8 9 10 11 12 13 14 15 16 17 18 5 6 7 8 9 10 v cc oe/rst feedback 1 2 3 4 20 19 18 17 16 15 14 13 q4 12 11 gnd q/2 ref_sel sync(0) v cc (an) lf v cc gnd q3 v cc q2 gnd gnd(an) lock q5 2q 21 22 23 24 sync(1) freq_sel gnd q0 v cc q1 gnd pll_en 25 26 27 28 ssop top view plcc top view pin name i/o description sync(0) i reference clock input sync(1) i reference clock input ref_sel i chooses reference between sync (0) & sync (1) (refer to functional block diagram) freq_sel i selects between 1 and 2 frequency options (refer to functional block diagram) feedback i feedback input to phase detector lf i input for external loop filter connection q0-q4 o clock output q5 o inverted clock output 2q o clock output (2 x q frequency) q/2 o clock output (q frequency 2) lock o indicates phase lock has been achieved (high when locked) oe/ rst i asynchronous reset (active low) and output enable (active high). when high, outputs are enabled. when low, outputs are in high impedance. pll_en i disables phase-lock for low frequency testing (refer to functional block diagram)
commercial temperature range idt74fct388915t 3.3v low skew pll-based cmos clock driver (3-state) 3 symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to +4.6 v v term (3) terminal voltage with respect to gnd ?0.5 to +7 v v term (4) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?60 to +60 ma absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. vcc terminals. 3. input terminals. 4. outputs and i/o terminals. symbol parameter conditions typ. max. unit c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 5.5 8 pf capacitance (t a = +25c, f = 1.0mhz) symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2 ? 5.5 v v il input low level guaranteed logic low level ? ? 0.8 v i ih input high current (4) v cc = max. v i = 5.5v ? ? 1a i il input low current (4) v cc = max. v i = gnd ? ? 1a i ozh high impedance output current (4) v cc = max. v i = v cc ?? 1a i ozl (3-state output pins) v i = gnd ? ? 1 v ik clamp diode voltage v cc = min., i in = ?18ma ? ?0.7 ?1.2 v i odh output drive current v cc = min., v in = v ih or v il, v o = 1.5v (3) ?36 ? ? ma i odl output drive current v cc = min., v in = v ih or v il, v o = 1.5v (3) 50 ? ? m a v oh output high voltage v cc = min i oh = ?16ma 2.4 (4) 3.3 ? v v ol output low voltage v cc = min i ol = 32ma ? 0.3 0.5 v v h input hysteresis ? ? 100 ? mv i ccl quiescent power supply current v cc = max.,v in = gnd or v cc ?2 6a i cch (test mode) i ccz dc electrical characteristics over operating range following conditions apply unless otherwise specified: commercial: t a = 0c to +70c, v cc = 3.3v 0.3v notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 3.3v, +25c ambient. 3. not more than one output should be tested at one time. duration of the test should not exceed one second. 4. v oh = v cc - 0.6v at rated current.
commercial temperature range 4 idt74fct388915t 3.3v low skew pll-based cmos clock driver (3-state) power supply characteristics symbol parameter test conditions (1) min. typ. (2) max. unit ? i cc quiescent power supply current v cc = max. v in = v cc ?0.6v (3) ?230a ttl inputs high v in = v cc ?2.1v (3) i ccd dynamic power supply current (4) v cc = max. v in = v cc ? 0.2 0.3 ma/ all outputs open v in = gnd mhz c pd power dissipation capacitance 50% duty cycle ? 15 25 pf i c total power supply current (6) v cc = max. ? 30 60 ma pll_en = 1, lock = 1, feedback = q4 sync frequency = 50mhz. all bits loaded with 15pf v cc = max. ? 90 120 ma pll_en = 1, lock = 1, feedback = q4 sync frequency = 50mhz. all bits loaded with 50 ? thevenin termination and 20pf notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 3.3v, +25c ambient. 3. per ttl driven input. all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. it is derived with q fre quency as the reference. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + di cc d h n t + i ccd (f) + i load i cc = quiescent current (i ccl , i cch and i ccz ) ? i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f = 2q frequency i load = dynamic current due to load. output frequency specifications max. (2) symbol parameter min. 70 100 133 (3) 150 (3) unit f2q operating frequency 2q output 40 70 100 133 150 mhz fq operating frequency q0-q4, q 5 outputs 20 35 50 66.7 75 m h z fq/2 operating frequency q/2 output 10 17.5 25 33.3 37.5 m h z synch input timing requirments symbol parameter min. max. unit t rise/fall rise/fall times, sync inputs ? 3 ns (0.8v to 2v) frequency input frequency, sync inputs 10 (1) 2q fmax mhz duty cycle input duty cycle, sync inputs 25% 75% ? notes: 1. note 7 in "general ac specification notes" and figure 3 describes this specification and its actual limits depending on the f eedback connection. 2. maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded. 3. at this frequency, 2q cannot be used as feedback.
commercial temperature range idt74fct388915t 3.3v low skew pll-based cmos clock driver (3-state) 5 switching characteristics over operating range symbol parameter condition (1) min . max. unit t rise/fall rise/fall time load = 50 ? to v cc /2, c l = 20pf 0.2 (2) 2ns all outputs (between 0.8v and 2v) t pulse width (3) output pulse width load = 50 ? to v cc /2, c l = 20pf 0.5t cycle ? 0.8 (5) 0.5t cycle + 0.8 (5) ns q, q , q/2 outputs (3) q0-q4, q 5, q/2, @ 1.5v t pulse width output pulse width 0.5t cycle ? 1 (5) 0.5t cycle + 1 (5) ns 2q output (3) 2q @ 1.5v t pd sync input to feedback delay load = 50 ? to v cc /2, c l = 20pf +0.1 +1.3 ns sync-feedback (3) (measured at sync0 or 1 and feedback input pins) 0.1f from lf to analog gnd (5) t skew r output to output skew between outputs 2q, q0-q4, load = 50 ? to v cc /2, c l = 20pf ? 600 ps (rising) (3,4) q/2 (rising edges only) t skew f output to output skew ? 250 ps (falling) (3,4) between outputs q0-q4 (falling edges only) t skew all (3,4) output to output skew ? 800 ps 2q, q/2, q0-q4 rising, q 5 falling t lock (6) time required to acquire phase-lock from time 1 (2) 10 ms sync input signal is received t pzh output enable time 3 (2) 14 ns t pzl oe/ rst (low-to-high) to q, 2q, q/2, q t phz output disable time 3 (2) 14 ns t plz oe/ rst (high-to-low) to q, 2q, q/2, q general ac specification notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested. 3. these specifications are guaranteed but not production tested. 4. under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage. 5. t cycle = 1/frequency at which each output (q, q , q/2 or 2q) is expected to run. 6. with v cc fully powered-on and an output properly connected to the feedback pin, t lock max. is with c1 = 0.1f, t lock min. is with c1 = 0.01f. (where c1 is loop filter capacitor shown in figure 2). 7. the wiring diagrams and written explanations of figure 3 demonstrate the input and output frequency relationships for various possible feedback configurations. the allowable sync input range to stay in the phase-locked condition is also indicated. there are two allowable sync frequency ranges, depen ding on whether freq_sel is high or low. also it is possible to feed back the q5 output, thus creating a 180 phase shift between the sync input and the q outputs. the table below summarizes the allowable sy nc frequency range for each possible configuration. freq_sel feedback allowable sync input corresponding 2q output phase relationship of the q outputs level output frequency range (mhz) frequency range to rising sync edge high q/2 10 to (2x_q f max spec)/4 40 to (2q f max spec) 0 high any q (q0-q4) 20 to (2x_q f max spec)/2 40 to (2q f max spec) 0 high q5 20 to (2x_q f max spec)/2 40 to (2q f max spec) 180 high 2x_q 40 to (2x_q f max spec) 40 to (2q f max spec) 0 low q/2 5 to (2x_q f max spec)/8 20 to (2q f max spec)/2 0 low any q (q0-q4) 10 to (2x_q f max spec)/4 20 to (2q f max spec)/2 0 low q5 10 to (2x_q f max spec)/4 20 to (2q f max spec)/2 180 low 2x_q 20 to (2x_q f max spec)/2 20 to (2q f max spec)/2 0
commercial temperature range 6 idt74fct388915t 3.3v low skew pll-based cmos clock driver (3-state) general ac specification notes (continued): 8. the tpd spec describes how the phase offset between the sync input and the output connected to the feedback input, varies wi th process, temperature and voltage. the phase measurements were made at 1.5v. the q/2 output was terminated at the feedback input with 100 ? to v cc and 100 ? to ground. tpd measurements were made with the loop filter connection shown in figure 1 below: analog loop filter section of the fct388915t analog v cc analog gnd lf board gnd board v cc 0.1 f (loop filter cap) 0.1 f high freq. bypass 10 f low freq. bypass a separate analog power supply is not necessary and should not be used. following these pre- scribed guidelines is all that is necessary to use the fct388915t in a normal digital environment. lf external loop filter 0.1 f c1 analog gnd figure 2. recommended loop filter and analog isolation scheme for the fct388915t notes: 1. figure 2 shows a loop filter and analog isolation scheme which will be effective in most applications. the following guideli nes should be followed to ensure stable and jitter-free operation: a. all loop filter and analog isolation components should be tied as close to the package as possible. stray current passing t hrough the parasitics of long traces can cause undesirable voltage transients at the lf pin. b. the 10f low frequency bypass capacitor and the 0.1f high frequency bypass capacitor form a wide bandwidth filter that will minimize the 388915t's sensitivity to voltage transients from the system digital v cc supply and ground planes. if good bypass techniques are used on a board design near components which may cause digital v cc and ground noise, v cc step deviations should not occur at the 388915t's digital v cc supply. the purpose of the bypass filtering scheme shown in figure 2 is to give the 388915t additional protection from the p ower supply and ground plane transients that can occur in a high frequency, high speed digital system. c. the loop filter capacitor (0.1f) can be a ceramic chip capacitor, the same as a standard bypass capacitor. 2. in addition to the bypass capacitors used in the analog filter of figure 2 there should be a 0.1f bypass capacitor between e ach of the other (digital) four v cc pins and the board ground plane. this will reduce output switching noise caused by the 388915t outputs, in addition to reducing potential for noi se in the "analog" section of the chip. these bypass capacitors should also be tied as close to the 388915t package as possible. figure 1
commercial temperature range idt74fct388915t 3.3v low skew pll-based cmos clock driver (3-state) 7 the frequency relationship shown here is applicable to all q outputs (q0, q1, q2, q3 and q4). 1:2 input to "q" output frequency relationship in this application, the q/2 output is connected to the feedback input. the internal pll will line up the positive edges of q/2 and sync, thus the q/2 frequency will equal the sync frequency. the q outputs (q0-q4, q5 ) will always run at 2x the q/2 frequency, and the 2q output will run at 4x the q/2 frequency. 1:1 input to "q" output frequency relationship in this application, the q4 output is connected to the feedback input. the internal pll will line up the positive edges of q4 and sync, thus the q4 frequency (and the rest of the "q" outputs) will equal the sync frequency. the q/2 output will always run at 1/2 the q frequency, and the 2q output will run at 2x the q frequency. allowable input frequency range: 40mhz to (f2q max spec) (for freq_sel high) 20mhz to (f2q max spec)/2 (for freq_sel low) allowable input frequency range: 20mhz to (f2q max spec)/2 (for freq_sel high) 10mhz to (f2q max spec)/4 (for freq_sel low) 2:1 input to "q" output frequency relationship in this application, the 2q output is connected to the feedback input. the internal pll will line up the positive edges of 2q and sync, thus the 2q frequency will equal the sync frequency. the q/2 output will always run at 1/4 the 2q frequency, and the q output will run at 1/2 the 2q frequency. figure 3a. wiring diagram and frequency relationships with q/ 2 output feedback figure 3c. wiring diagram and frequency relationships with 2q output feedback figure 3b. wiring diagram and frequency relationships with q4 output feedback allowable input frequency range: 10mhz to ( f2q max spec)/4 (for freq_sel high) 5mhz to (f2q max spec)/8 (for freq_sel low) q/2 q3 q2 pll_en q1 q0 fq_sel feedback ref_sel sync(0) v cc (an) gnd(an) q4 q5 2q low 50 mhz signal 12.5 mhz feedback signal high high high 25 mhz "q" clock outputs 12.5 mhz input lf fct388915t rst oe/ q/2 q3 q2 pll_en q1 q0 fq_sel feedback ref_sel sync(0) v cc (an) gnd(an) q4 q5 2q low 50 mhz signal 25 mhz feedback signal high high high 25 mhz "q" clock outputs 25 mhz input 12.5 mhz signal lf fct388915t rst oe/ q/2 q3 q2 pll_en q1 q0 fq_sel feedback ref_sel sync(0) v cc (an) gnd(an) q4 q5 2q low 50 mhz feedback signal high high high 25 mhz "q" clock outputs 50 mhz input 12.5 mhz input lf fct388915t rst oe/
commercial temperature range 8 idt74fct388915t 3.3v low skew pll-based cmos clock driver (3-state) cmmu cmmu cpu cmmu cmmu cmmu cmmu cmmu cpu cmmu cmmu cmmu pll 2f pll 2f cpu card cpu card clock @f system clock source fct388915t fct388915t distribute clock @f clock @2f at point of use memory control pll 2f memory cards clock @2f at point of use fct388915t figure 4. multiprocessing application using the fct388915t for frequency multiplication and low board-to-board skew fct388915t system level testing functionality when the pll_en pin is low, the pll is bypassed and the fct388915t is in low frequency "test mode". in test mode (with freq_sel high), the 2q output is inverted from the selected sync input, and the q outputs are divide- by-2 (negative edge triggered) of the sync input, and the q/2 output is divide- by-4 (negative edge triggered). with freq_sel low the 2q output is divide- by-2 of the sync, the q outputs divide-by-4, and the q/2 output divide-by-8. these relationships can be seen in the block diagram. a recommended test configuration would be to use sync0 or sync1 as the test clock input, and tie pll_en and ref_sel together and connect them to the test select logic. this functionality is needed since most board-level testers run at 1 mhz or below, and thefct 388915t cannot lock onto that low of an input frequency. in the test mode described above, any test frequency test can be used.
commercial temperature range idt74fct388915t 3.3v low skew pll-based cmos clock driver (3-state) 9 t sync input t "q" outputs t tt t t pd sync input (sync (1) or sync (0)) feedback input q/2 output q0-q4 outputs q5 output 2q output t skewf skewr skewf skewall skewr cycle cycle 1.5v v cc/2 v cc/2 v cc/2 v cc/2 v cc/2 control input 3v 1.5v 0v 3v 0v output normally low output normally high switch 6v switch gnd v ol 0.3v 0.3v t plz t pzl t pzh t phz 3v 0v 1.5v 1.5v enable disable v oh pulse generator d.u.t. v cc v in v out 100 ? 100 ? r t v cc 20pf c l pulse generator d.u.t. v cc v in v out 500 ? gnd 6.0v 500 ? r t (these waveforms represent the configuration of figure 3a) notes: 1. the fct388915t aligns rising edges of the feedback input and sync input, therefore the sync input does not require a 50% dut y cycle. 2. all skew specs are measured between the v cc /2 crossing point of the appropriate output edges. all skews are specified as "windows", not as deviation around a center po int. 3. if a q ouput is connected to the feedback input (this situation is not shown), the q output frequency would match the sync in put frequency, the 2q output would run at twice the sync frequency and the q/2 output would run at half the sync frequency. propagation delay, output skew test circuits and waveforms test switch disable low 6v enable low disable high gnd enable high switch position definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. diagram shown for input control enable-low and input control disable-high. 2. pulse generator for all pulses: t f 2.5ns; t r 2.5ns. enable and disable times enable and disable test circuit 50 ? ? ? ? ? to v cc /2, c l = 20pf
commercial temperature range 10 idt74fct388915t 3.3v low skew pll-based cmos clock driver (3-state) ordering information xxxx device type package j jg py pyg 388915t plastic leaded chip carrier plcc - green small shrink outline ic ssop - green 3.3v low skew pll-based cmos clock driver xx speed 70 100 133 150 70mhz max. frequency 100mhz max. frequency 133mhz max. frequency 150mhz max. frequency xx fct idt xx temp. range 74 0c to +70c corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com
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